By David Robert Stauffer, Jeanne Trinko Mechler, Michael A. Sorna, Kent Dramstad, Clarence Rosser Ogilvie, Amanullah Mohammad, James Donald Rockrohr
High pace Serdes units and Applications offers a huge figuring out of excessive velocity Serdes (HSS) equipment utilization. the cloth makes a speciality of HSS units, and the consolidation of similar issues right into a unmarried textual content. Chip and procedure designers utilizing HSS units should have exact wisdom of either the positive aspects and features of the HSS gadget, and the functions within which they're used. additionally designers should have a operating wisdom of similar matters, together with: reference clock architectures, sign integrity, strength dissipation, and try good points and services. The authors consolidate those issues with a particular concentrate on HSS units. This process offers the chip dressmaker adequate history info for utilizing HSS units on their chips.
The chapters could be seen as 4 precise sections. the 1st part pertains to the gains, capabilities, and layout of HSS units. moment are chapters that describe the beneficial properties and services of protocol good judgment used to enforce a variety of community protocol interface criteria. The 3rd part covers really good issues relating to HSS cores. eventually, features of commonplace layout package versions to facilitate integration in the chip layout are discussed.
High pace Serdes units and Applications is an invaluable source for chip designers utilizing HSS units of their chip design.
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Additional info for High Speed Serdes Devices and Applications
Each impedance discontinuity results in reflections of the electrical energy. As with any transmission line, reflected energy adds to or subtracts from the signal amplitude at various points along the transmission line, and results in resonances in the transfer function. This signal degradation is generally worse for shorter channel lengths; loss characteristics of longer channels tend to dampen reflections whereas signals may reflect between the transmitter and receiver multiple times on a short channel.
However for some DFE designs this may not be a single node, or may be beyond the point where analog-to-digital conversion of the signal has been performed. The notion of an analog “eye” at this point is a virtual mathematical concept; this eye is not a measurable analog signal. Note that signal integrity engineers often prefer to view analysis results in the form of a bathtub curve which graphs eye opening as a function of Q of the system (which relates to BER), as is described further in Sect.
If the “eye” is sufficiently “open” for the desired BER, then the system will operate with no more than the specified number of bit errors. The terminology “eye” is used loosely in the above paragraph, hence the quotation marks. The receiver device often contains a DFE. By convention, the “eye” is the signal at the sampling latch of a classical DFE design. However for some DFE designs this may not be a single node, or may be beyond the point where analog-to-digital conversion of the signal has been performed.